Broadcast video desynchronizer

ABSTRACT

An arrangement for desynchronizing video signals transported in virtual containers in frames over a synchronous network comprises a feedback loop incorporating a FIFO buffer store and a tuneable oscillator adapted to provide a video line clock from demapped video information. Each virtual container is identified within a frame by a pointer introduced by the synchronous transport process, and the loop is arranged to overcome the interference of these pointers with the color subcarrier in the desynchronized signal. The loop has a bandwidth sufficiently narrow to effectively ignore phase noise created by the pointers. The oscillator frequency is controlled such that the rate of information flow around the loop is substantially constant. Video bytes are written into the buffer store and are then read at a controlled rate determined by the oscillator frequency.

This invention relates to the provision of television or video serviceson a synchronous network, and in particular to the desynchronisation ofsuch services at a user station.

BACKGROUND OF THE INVENTION

The provision of 34 Mbits television services on the synchronous networkrequires stringent control of low frequency phase at the desynchroniser.As 34 M video codecs linearly encode the colour sub carrier of the PALsignal, any phase disturbances introduced by the synchronous transport(e.g. SDH) network propagate through the codec and into thereconstituted video. There are two bounding parameters that the videonetwork providers consider to be important to deliver an acceptablequality of service to customers. First the phase transients in the bitstream must be such that the colour sub carrier, at 4.43 MHz will haveno greater than a 0.1 Hz per second rate of change. Second, the delaybudget in a telephony link must be no more than 100 microseconds. Thefinal parameter of interest in bounding the desynchroniser system isthat the network requires a minimum of 30 s to set up a connection. Thisis very much a worst case scenario, and more common switch times are inthe order of up to 30 minutes and more. The most difficult problem isthat of eliminating phase disturbances arising from the arrival of thevideo pointers which are used to bring the net flow of information backto the original input rate. A number of techniques have been proposed toaddress this problem, but none has been entirely successful.

A desynchroniser which uses the synchronous property of SONET todiminish the effect of pointer variations on an output clock phase isdescribed by S. Say in Bellcore Standard T1X1.6/88-026, Jul. 25, 1988,pages 2 to 9.

SUMMARY OF THE INVENTION

According to one aspect of the invention there is provided anarrangement for desynchronising video signals broadcast over asynchronous network, the arrangement including means for demapping inputvideo information, a feedback control loop incorporating afirst-in-first-out (FIFO) buffer store into which the demapped videoinformation bytes are written and from which said bytes are read, saidstore having a first wriite input for the demapped information, a secondread input and an output, an amplifier coupled to the output of thebuffer store, a tuneable oscillator adapted to provide a video lineclock from the demapped video information and coupled to the output ofthe amplifier via a transfer function circuit, and an integrator coupledto the oscillator and to the read input of the FIFO buffer so as toclose the feedback loop and so as to determine the fill depth of theFIFO buffer, said fill depth providing an error reference for thefeedback control loop, there being means for controlling the oscillatorfrequency and for reading the video information from the store at a ratedetermined by the oscillator frequency such that the rate of informationflow around the feedback control loop is substantially constant.

According to a further aspect of the invention there is provided amethod for desynchronising video signals broadcast over a synchronousnetwork incorporating a feedback control loop having afirst-in-first-out (FIFO) buffer store having read and write inputs andinto which received video bytes are written and from which said bytesare read, an amplifier coupled to the output of the buffer store, atuneable oscillator adapted to provide a video line clock from thedemapped video information and coupled to the output of the amplifiervia a transfer function circuit, and an integrator coupled to theoscillator and to the read input of the FIFO buffer so as to close thefeedback loop and so as to determine the fill depth of the FIFO buffer,the method including demapping said received video information, writingthe demapped video information into the wriite input of said bufferstore, providing an error reference signal for the feedback control loopfrom the fill depth of the FIFO buffer, and controlling the oscillatorfrequency and reading the video information from the store at a ratedetermined by the oscillator frequency such that the rate of informationflow around the feedback control loop is substantially constant.

Reference is here directed to our United Kingdom specification No. No.2,283,885 which relates to a method of controlling the leakage of apointer for a pointer justification event (PJE) at the exit from asynchronous transport network to a plesiochronous tributary when videoservices are carried on the network. In that application, the leak rateof a primary buffer is modulated in a manner whereby the rate of changeleak rate is dependent on the rate of arrival of PJE's.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the invention will now be described with reference tothe accompanying drawings in which:

FIG. 1 is a schematic diagram of a synchronous network provided withvideo broadcast facilities; and

FIG. 2 is a schematic diagram of a desynchroniser arrangement for use inthe network of FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENT

Referring to FIG. 1, video information from a transmitter station 10 ismapped into virtual containers via a codec 11 for transmission acrossthe synchronous network 12. At the receiving station or user terminal14, the video information in the arriving containers is demapped via acodec 13 and is then fed to the user terminal for display. The processfor recovering the video information is described with reference to FIG.2 below.

Referring to FIG. 2, low frequency phase control is provided by anarrangement based on a control loop. This loop uses the incoming C3demapped information stream to control the frequency of a voltagecontrolled oscillator, e.g. a crystal oscillator (VCXO), which in turnprovides the 34M line clock. We have found that this arrangementoperates effectively, as the phase noise due to pointer and otheractivities in the information flow into the control loop is outside thebandwidth of the loop. Thus, incoming phase noise appears on the outputas a ripple. The loop is therefore designed to maintain this ripplewithin the video parameters.

The loop comprises a FIFO buffer 21 which accepts bytes arriving atinput port 20 from the C3 demapping function and provides a controlsignal via an amplifier 22 and a transfer function circuit 23 to theoscillator 25. The oscillator output is fed back via an integrator 26 toa second input of the FIFO buffer. The fill depth of the buffer is theerror reference used by the control loop. This error is filtered andgoes through a digital to analogue conversion to provide the input driveto the oscillator 25. This oscillator is used to read the bytes from theFIFO and provides the reconstituted line clock at output port 27.

The principle of operation of the loop is that the rate of informationflow is substantially constant. That is to say that the original inputto the synchronous network is from a serial 34M bit stream and the bitrate of this is effectively encoded in the justification pattern of theincoming C3 information stream and in the pointer activity. Thus when anSDH frequency offset comes into play, the arriving pointers operate tobring the net flow of information back to the original input rate. Forexample, if the receiving node is receiving an AU4 at +3 ppm, the rateof arrival will be too high. The node will re transmit with negativepointer justifications keeping the average information flow rateconstant. The pointer activity may thus be viewed as phase disturbanceon the 34M serial bit stream.

The amplitude of the phase disturbances has two parts. One part isconsequential to the SDH framing and is entirely predictable. The otheris the pointer amplitude which is, in the worst case, 8 bits. As thetime constant of the control loop is relatively long, a sampled digitalsystem may have a low sampling interval, and for validity, the samplingshould occur at a point where the input is stable. This occurs duringthe section overhead part of the frame. The maximum sampling ratepossible in this scheme is thus on a per row basis giving 72 kHz.

The loop may be described by the phase transfer function ##EQU1##

Assuming that the worst step height will be 16 bits, this function maybe used to design the loop. The worst case of 16 bits is based on twicethat which would be expected from a pointer. The response to a step isgiven by multiplying through by K/s and transferring back into the timedomain. There are two roots to the denominator. These roots are given as##EQU2##

In a critically, or over damped system the loop transfer function in theform ##EQU3## gives the roots as ##EQU4##

The optimal system will be one where the response is critically damped.From equation 3 above, the step response will be ##EQU5## where K is thestep height. This equation is of the form ##EQU6## With n=2 and a=ω₁₁.Thus the time domain response to a step input is

    Φ.sub.0 =Kω.sub.11.sup.2 (t.sub.e.sup.31 ωd)(7)

The parameter of interest in the desynchroniser for video use, is therate of change of phase. This can be found from differentiating equation(7) with respect to time giving

    Φ.sub.0 =Kω.sub.11.sup.2 (-ω.sub.11 t.sub.e.sup.-ωd +e.sup.-ωd)                                         (8)

The maximum of the modulus of Φ₁₁ will occur when t=0. Therefore

    Φ.sub.0 =Kω.sub.11.sup.2                         (9)

Going back to the video specification of 0.1 Hz per second at 4.43 MHz,this can be expressed as 0.0225 ppm/s and applied to any carrier rate.At the 34.368 Mbit carrier rate, and using 0.0223 ppm/s for margin, thiscorresponds to 0.76 bits, or 0.76 Ul per second. This is Φ_(0max). So inresponse to a 16 bit step, K=16 and ω₁₁ is derived as 0.22 rad/s. Usingthe format of equation 5 in equation 3 the values of the time constantand gain follow as 0.44 and 0.11 respectively.

For final implementation of the circuit, some boundaries may be defined.The VCXO should preferably have a gain typically of 50 ppm/V. Thus themaximum swing may be + or -2.0V about a 2.5V mean. The overall VCXO gainincludes a scalar for the centre frequency, as the deviation is a fewparts per million of the centre frequency. Therefore the gain may besplit into three components, G₁ the calculated gain, G_(v) the VCXO gainin ppm/V and G_(f) the centre frequency component. Thus 0.109=G₁ G_(v)G_(f). Solving for G₁, we have ##EQU7##

When in use the loop will effectively be driven by a phase ramp. TheVCXO responds to the difference between the information flow rate intothe FIFO from the C3, and its own centre frequency. Therefore, in thesteady state, a static error is present in the buffer representing thedrive voltage to maintain the offset.

The step input to the system is given as amplitude 16 bits. The rate ofchange of frequency is detected by the du/dt term and the outputresponse gives an initial rate of change of frequency of 0.76. Thefrequency performance of the loop may be determined by providing aninput ramp. In this case, the interesting activity is the response ofthe system to a step change in input frequency. Such conditions canoccur in the network if a user switches the 34M line from one source toanother. This may give a theoretical maximum step change of 40 ppm.

The initial conditions of the FIFO buffer 21 are set to leave enoughroom for the step inputs to go to the positive or negative limits. Themaximum allowable step change in input is given by the 34M line beingswitched from a -20 ppm line to a +20 ppm line. This gives a step inputof 40 ppm swing. This will always be the maximum amplitude and a firstapproximation of the FIFO depth requirements are to equal this with acentre at the mid point. Using a 40 ppm step the max. fill is given as##EQU8## This is solved to give a step amplitude of 12699 bits, or 1588bytes.

Consideration should also be given to the steady state error introducedby the variation in centre frequency of the VCXO. Taking this to betypically +/-25 ppm, the swing from this is greater than the input linefrequency. The effect of this is to skew the FIFO fill about a point notequal to the mid point. For example, if the VCXO is supplied with anopen loop centre frequency of +25 ppm, this would mean that the outputfrequency would be at +25 ppm offset when the input voltage was at 2.5V.Thus to drive a nominal 0 ppm line offset, a steady state drive voltageof 0.5V is required. This 0.5 V will correspond to a buffer "fill" of7936 bits.

In a practical implementation, the FIFO will be given a fixed centre,such that the fill, during any of the input conditions will never causethe read and write address printers to coincide or crash. Therefore inthe sample case this will be equal to half the maximum swing amplitudeplus a margin for frame jitter and pointer bursts. Nominally this willbe 794 bytes, from the solution to equation 11. However, if a steadystate error exists, this will form an additional offset to the FIFOcentre. A preferred way of overcoming this is to use the fact that thecentre frequency is a steady state value which may be tuned out atmanufacture. This may be effected by providing an additional steadystate error register which is used at manufacture to set the open loopcentre frequency. This value is stored in non volatile memory andwritten to the mapper at power up. The magnitude of the steady stateerror is important to balance against the dynamic range of the VCXO. The+/-25 ppm variation corresponds to a maximum of 1V of range required ona 50 ppm/V device. The available dynamic range for line tracking istherefore reduced to 3V as +/-1.5V. At 50 ppm this allows for 150 ppmtracking which can adequately cover the line variations in a secondorder control system. However, this is just inside the limit for themore complex control situation following. (A 30 ppm VCXO would beunsuitable, as the 50 ppm variation would require 1.8V to tune out. Thiswould leave a range of 2.2V corresponding to 66 ppm. This is just overthe required 40 ppm, but would not allow the following cases tofunction).

The primary limiting factor in the second order loop is the staticerror. This should not be confused with the previously described steadystate error. The static error is that generated by the frequencydeviation of the 34M line. This deviation causes a residual fill in thebuffer which in turn drives the VCXO in the closed loop control system.This error is constant, after settling, and directly proportional todelay (with a constant of proportionality of 2.91×10⁻⁸ seconds per bitat 34.368 Mbit/s line rate). With the system simulated, a FIFO size of1588 bytes is required centred about 794 bytes. The delay through thissystem is be determined by the fill state of the buffer, which in turnis determined by the input frequency deviation. A deviation of -20 ppmwill have a nominally zero delay and a deviation of +20 ppm will havenominally 370 microseconds. The 100 microsecond maximum delayspecification is therefore compromised. It is preferred to remove thedelay dependence on input frequency deviation by eliminating the staticerror.

In order to drive the static error to zero it is necessary to provideeffectively an "imaginary" static error. This takes the form ofproviding a drive to the VCXO when the system has settled to zero errorin the buffer. An integrator is therefore necessary to provide an outputwhen its input is zero. This turns the loop into a third order system bysumming the integral of the error scaled to the filtered scaled errorterm driving the VCXO. The characteristic equation is now given as##EQU9##

Note that when the scalar K is set to zero, the characteristic resumesto the second order original of equation 1. The effect of the integralterm may be kept to a minimum if the constant scalar K is around anorder of magnitude less than G. Both of these constants are compound,and both share the terms, G_(v) and G_(f), so the effect can only beachieved by setting K₁ an order of magnitude or so less than G₁.

The simplest means of ensuring a better than 0.76 ppm/s step response,is to add the third order gain term at tenth gain in parallel with thesecond order term and adjust on resulting simulations of 16 bit stepresponses. The time constant required reduction and the gain of theintegrating term were reduced to approximately a thirtieth. The methodused here was to adjust the gain down until the roots of the denominatorof the third order polynomial in s become real. This gives a dampingfactor of 1 and the third order loop is accordingly critically damped.

What is claimed is:
 1. An arrangement for desynchronizing video signalstransported in virtual containers in frames and received from asynchronous network, each virtual container being identified within asaid frame by a pointer introduced by the synchronous transport process,the arrangement comprising means for demapping input video informationfrom said frames so as to recover video information bytes, a phaselocked control loop system having a bandwidth sufficiently narrow toeffectively ignore phase noise created by the pointers and incorporatinga first-in-first-out (FIFO) buffer store into which the demapped videoinformation bytes are written, said store having a first write input forstoring the demapped information at the rate at which that informationis demapped, a second read input and an output, an amplifier coupled tothe output of the buffer store, a voltage controlled oscillator havingan output and having a control input coupled to the output of theamplifier via a transfer function circuit and said output controllingvia a feedback path incorporating an integrator to said read input ofsaid buffer store the rate at which stored video information is readfrom the buffer store such that the rate of information flow around thefeedback control loop is substantially uniform, said oscillator beingarranged to provide a video line clock from the read video information,and wherein the fill depth of the FIFO buffer store, provides an errorreference for the voltage controlled oscillator frequency so as toincrease or decrease that frequency as said fill depth increases ordecreases respectively.
 2. An arrangement as claimed in claim 1, whereinsaid oscillator is a voltage controlled crystal oscillator having afrequency variation of about 25 parts per million about a centrefrequency.
 3. A telecommunications subscriber terminal provided with avideo desynchronising arrangement as claimed in claim
 1. 4. A method fordesynchronizing video signals transported in virtual containers inframes and received from a synchronous network, each virtual containerbeing identified within a said frame by a pointer introduced by thesynchronous transport process; the method comprising; demapping inputvideo information from said frames so as to recover video informationbytes, writing said demapped video information at the rate at which thatinformation is demapped into a first-in-first-out (FIFO) buffer storehaving a read input, a write input and an output, said buffer storeforming part of a phase locked control loop system incorporating avoltage controlled oscillator having a control input and an output, saidloop having a bandwidth sufficiently narrow to effectively ignore phasenoise created by the pointers, applying said oscillator output via anintegrator to said read input of the buffer store so as to control therate at which the demapped stored video information is read from thebuffer store such that the rate of information flow around the feedbackcontrol loop is substantially uniform, said oscillator being arranged toprovide a video line clock from the read video information, andproviding to the oscillator control input via a transfer function acontrol voltage corresponding to the fill depth of the buffer store soas to increase or decrease the oscillator frequency as said fill depthincreases or decreases respectively.
 5. A method as claimed in claim 4,wherein said voltage controlled oscillator has a frequency variation ofabout 25 parts per million about a centre frequency.
 6. A method asclaimed in claim 5, wherein said buffer store has an average fill depthskewed from a half full condition.